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1 1 2 3 4 8 7 6 5 cs so wp gnd vcc hold sck si 8-lead pdip 1 2 3 4 8 7 6 5 cs so wp gnd vcc hold sck si 8-lead soic 1 2 3 4 8 7 6 5 cs so wp gnd vcc hold sck si 8-lead tssop 1 2 3 4 8 7 6 5 vcc hold sck si cs so wp gnd 8-lead sap vcc hold sck s i cs so wp gnd 1 2 3 4 8 7 6 5 8-ball dbga2 bottom view bottom view features ? serial peripheral interface (spi) compatible supports spi modes 0 (0,0) and 3 (1,1) data sheet describes mode 0 operation low-voltage and standard-voltage operation ? 2.7 (v cc = 2.7v to 5.5v) ? 1.8 (v cc = 1.8v to 5.5v) 20 mhz clock rate (5v) 64-byte page mode and byte write operation block write protection ? protect 1/4, 1/2, or entire array write protect (wp ) pin and write disable instructions for both hardware and so ftware data protection self-timed write cycle (5 ms max) high-reliability ? endurance: 1 million write cycles ? data retention: >100 years automotive grade, extended temp erature and lead-free/halogen-free devices available 8-lead pdip, 8-lead eiaj so ic, 8-lead jedec soic, 8-lead tssop, 8-ball dbga2 and 8-lead sap packages die sales: wafer form, wa ffle pack, and bumped die description the at2512 8 a/256a provides 1 3 1,072/262,144 bits of seri a l electric a lly-er a s a ble progr a mm a ble re a d only memory (eeprom) org a nized a s 16, 38 4/ 3 2,76 8 words of 8 bits e a ch. the device is optimized for use in m a ny industri a l a nd commerci a l a ppli- c a tions where low-power a nd low-volt a ge oper a tion a re essenti a l. the devices a re a v a il a ble in sp a ce s a ving 8 -le a d pdip, 8 -le a d eiaj s oic, 8 -le a d jedec s oic, 8 - le a d t ss op, 8 -b a ll dbga2 a nd 8 -le a d s ap p a ck a ges. in a ddition, the entire f a mily is a v a il a ble in 2.7v (2.7v to 5.5v) a nd 1. 8 v (1. 8 v to 5.5v) versions. the at2512 8 a/256a is en a bled through the chip s elect pin (c s ) a nd a ccessed vi a a 3 -wire interf a ce consisting of s eri a l d a t a input ( s i), s eri a l d a t a output ( s o), a nd s eri a l clock ( s ck). all progr a mming cycles a re completely self-timed, a nd no sep a - r a te er a se cycle is required before write. table 1. pin configur a tions pin name function c s chip s elect s ck s eri a l d a t a clock s i s eri a l d a t a input s o s eri a l d a t a output gnd ground vcc power s upply wp write protect hold s uspends s eri a l input nc no connect 33 6 8 h? s eepr? 8 /05 spi serial eeproms 128k (16,384 x 8) 256k (32,768 x 8) at25128a at25256a
2 at25128a/256a 33 6 8 h? s eepr? 8 /05 block write protection is en a bled by progr a mming the st a tus register with top ?, top ? or entire a rr a y of write protection. s ep a r a te progr a m en a ble a nd progr a m dis a ble instructions a re provided for a ddition a l d a t a protection. h a rdw a re d a t a protection is pro- vided vi a the wp pin to protect a g a inst in a dvertent write a ttempts to the st a tus register. the hold pin m a y be used to suspend a ny seri a l communic a tion without resetting the seri a l sequence. figure 1. block di a gr a m note: 1. this p a r a meter is ch a r a cterized a nd is not 100% tested. absolute maximum ratings* oper a ting temper a ture ......................................? 55 c to +125 c *notice: s tresses beyond those listed under ?absolute m a xi- mum r a tings? m a y c a use perm a nent d a m a ge to the device. this is a stress r a ting only a nd function a l oper a tion of the device a t these or a ny other condi- tions beyond those indic a ted in the oper a tion a l sec- tions of this specific a tion is not implied. exposure to a bsolute m a ximum r a ting conditions for extended periods m a y a ffect device reli a bility. s tor a ge temper a ture .........................................? 65 c to +150 c volt a ge on any pin with respect to ground ........................................ ? 1.0v to +7.0v m a ximum oper a ting volt a ge .......................................... 6.25v dc output current........................................................ 5.0 ma 16384/32768 x 8 table 2. pin c a p a cit a nce (1) applic a ble over recommended oper a ting r a nge from t a = 25 c, f = 1.0 mhz, v cc = +5.0v (unless otherwise noted) symbol test conditions max units conditions c out output c a p a cit a nce ( s o) 8 pf v out = 0v c in input c a p a cit a nce (c s , s ck, s i, wp , hold )6pfv in = 0v
3 at25128a/256a 33 6 8 h? s eepr? 8 /05 note: 1. v il a nd v ih m a x a re reference only a nd a re not tested. table 3. dc ch a r a cteristics applic a ble over recommended oper a ting r a nge from t ai = ? 40c to + 8 5c, v cc = +1. 8 v to +5.5v, t ae = ? 40 c to +125 c, v cc = +1. 8 v to +5.5v(unless otherwise noted) symbol parameter test condition min typ max units v cc1 s upply volt a ge 1. 8 5.5 v v cc2 s upply volt a ge 2.7 5.5 v v cc 3 s upply volt a ge 4.5 5.5 v i cc1 s upply current v cc = 5.0v a t 20 mhz, s o = open, re a d 9.0 10.0 ma i cc2 s upply current v cc = 5.0v a t 10 mhz, s o = open, re a d, write 5.0 7.0 ma i cc 3 s upply current v cc = 5.0v a t 1 mhz, s o = open, re a d, write 2.2 3 .5 ma i s b1 s t a ndby current v cc = 1. 8 v, c s = v cc 0.2 3 .0 a i s b2 s t a ndby current v cc = 2.7v, c s = v cc 0.5 3 .0 a i s b 3 s t a ndby current v cc = 5.0v, c s = v cc 2.0 5.0 a i il input le a k a ge v in = 0v to v cc ? 3 .0 3 .0 a i ol output le a k a ge v in = 0v to v cc , t ac = 0 c to 70 c ? 3 .0 3 .0 a v il (1) input low-volt a ge ? 1.0 v cc x 0. 3 v v ih (1) input high-volt a ge v cc x 0.7 v cc + 0.5 v v ol1 output low-volt a ge 3 .6 v cc 5.5v i ol = 3 .0 ma 0.4 v v oh1 output high-volt a ge i oh = ? 1.6 ma v cc ? 0. 8 v v ol2 output low-volt a ge 1. 8 v v cc 3 .6v i ol = 0.15 ma 0.2 v v oh2 output high-volt a ge i oh = ? 100 a v cc ? 0.2 v table 4. ac ch a r a cteristics applic a ble over recommended oper a ting r a nge from t ai = ? 40 c to + 8 5 c, t ae = ? 40 c to +125 c, v cc = as s pecified, cl = 1 ttl g a te a nd 3 0 pf (unless otherwise noted) symbol parameter voltage min max units f s ck s ck clock frequency 4.5 ? 5.5 2.7 ? 5.5 1. 8 ? 5.5 0 0 0 20 10 5 mhz t ri input rise time 4.5 ? 5.5 2.7 ? 5.5 1. 8 ? 5.5 2 2 2 s t fi input f a ll time 4.5 ? 5.5 2.7 ? 5.5 1. 8 ? 5.5 2 2 2 s t wh s ck high time 4.5 ? 5.5 2.7 ? 5.5 1. 8 ? 5.5 20 40 8 0 ns
4 at25128a/256a 33 6 8 h? s eepr? 8 /05 note: 1. this p a r a meter is ch a r a cterized a nd is not 100% tested. cont a ct atmel for further inform a tion. t wl s ck low time 4.5 ? 5.5 2.7 ? 5.5 1. 8 ? 5.5 20 40 8 0 ns t c s c s high time 4.5 ? 5.5 2.7 ? 5.5 1. 8 ? 5.5 100 100 200 ns t c ss c s s etup time 4.5 ? 5.5 2.7 ? 5.5 1. 8 ? 5.5 100 100 200 ns t c s h c s hold time 4.5 ? 5.5 2.7 ? 5.5 1. 8 ? 5.5 100 100 200 ns t s u d a t a in s etup time 4.5 ? 5.5 2.7 ? 5.5 1. 8 ? 5.5 5 10 20 ns t h d a t a in hold time 4.5 ? 5.5 2.7 ? 5.5 1. 8 ? 5.5 5 10 20 ns t hd hold s etup time 4.5 ? 5.5 2.7 ? 5.5 1. 8 ? 5.5 5 10 20 ns t cd hold hold time 4.5 ? 5.5 2.7 ? 5.5 1. 8 ? 5.5 5 10 20 ns t v output v a lid 4.5 ? 5.5 2.7 ? 5.5 1. 8 ? 5.5 0 0 0 20 40 8 0 ns t ho output hold time 4.5 ? 5.5 2.7 ? 5.5 1. 8 ? 5.5 0 0 0 ns t lz hold to output low z 4.5 ? 5.5 2.7 ? 5.5 1. 8 ? 5.5 0 0 0 25 50 100 ns t hz hold to output high z 4.5 ? 5.5 2.7 ? 5.5 1. 8 ? 5.5 25 50 100 ns t di s output dis a ble time 4.5 ? 5.5 2.7 ? 5.5 1. 8 ? 5.5 25 50 100 ns t wc write cycle time 4.5 ? 5.5 2.7 ? 5.5 1. 8 ? 5.5 5 5 5 ms endur a nce (1) 5.0v, 25 c, p a ge mode 1m write cycles table 4. ac ch a r a cteristics (continued) applic a ble over recommended oper a ting r a nge from t ai = ? 40 c to + 8 5 c, t ae = ? 40 c to +125 c, v cc = as s pecified, cl = 1 ttl g a te a nd 3 0 pf (unless otherwise noted) symbol parameter voltage min max units
5 at25128a/256a 33 6 8 h? s eepr? 8 /05 serial interface description master: the device th a t gener a tes the seri a l clock. slave: bec a use the seri a l clock pin ( s ck) is a lw a ys a n input, the at2512 8 a/256a a lw a ys oper a tes a s a sl a ve. transmitter/receiver: the at2512 8 a/256a h a s sep a r a te pins design a ted for d a t a tr a nsmission ( s o) a nd reception ( s i). msb: the most s ignific a nt bit (m s b) is the first bit tr a nsmitted a nd received. serial op-code: after the device is selected with c s going low, the first byte will be received. this byte cont a ins the op-code th a t defines the oper a tions to be performed. invalid op-code: if a n inv a lid op-code is received, no d a t a will be shifted into the at2512 8 a/256a, a nd the seri a l output pin ( s o) will rem a in in a high imped a nce st a te until the f a lling edge of c s is detected a g a in. this will reiniti a lize the seri a l communic a tion. chip select: the at2512 8 a/256a is selected when the c s pin is low. when the device is not selected, d a t a will not be a ccepted vi a the s i pin, a nd the seri a l output pin ( s o) will rem a in in a high imped a nce st a te. hold: the hold pin is used in conjunction with the c s pin to select the at2512 8 a/256a. when the device is selected a nd a seri a l sequence is underw a y, hold c a n be used to p a use the seri a l communic a tion with the m a ster device without resetting the seri a l sequence. to p a use, the hold pin must be brought low while the s ck pin is low. to resume seri a l communic a tion, the hold pin is brought high while the s ck pin is low ( s ck m a y still toggle during hold ). inputs to the s i pin will be ignored while the s o pin is in the high imped a nce st a te. write protect: the write protect pin (wp ) will a llow norm a l re a d/write oper a tions when held high. when the wp pin is brought low a nd wpen bit is ?1?, a ll write oper a - tions to the st a tus register a re inhibited. wp going low while c s is still low will interrupt a write to the st a tus register. if the intern a l write cycle h a s a lre a dy been initi a ted, wp going low will h a ve no effect on a ny write oper a tion to the st a tus register. the wp pin function is blocked when the wpen bit in the st a tus register is ?0?. this will a llow the user to inst a ll the at2512 8 a/256a in a system with the wp pin tied to ground a nd still be a ble to write to the st a tus register. all wp pin functions a re en a bled when the wpen bit is set to ?1?.
6 at25128a/256a 33 6 8 h? s eepr? 8 /05 figure 2. s pi s eri a l interf a ce at2512 8 a/256a
7 at25128a/256a 33 6 8 h? s eepr? 8 /05 functional description the at2512 8 a/256a is designed to interf a ce directly with the synchronous seri a l peripher a l interf a ce ( s pi) of the 6 8 00 type series of microcontrollers. the at2512 8 a/256a utilizes a n 8 -bit instruction re gister. the list of instructions a nd their oper a tion codes a re cont a ined in see t a ble 5. all instructions, a ddresses, a nd d a t a a re tr a nsferred with the m s b first a nd st a rt with a high-to-low c s tr a nsition. write enable (wren): the device will power-up in the write dis a ble st a te when v cc is a pplied. all progr a mming instructions must therefore be preceded by a write en a ble instruction. write disable (wrdi): to protect the device a g a inst in a dvertent writes, the write dis a ble instruction dis a bles a ll progr a mming modes. the wrdi instruction is indepen- dent of the st a tus of the wp pin. read status register (rdsr): the re a d s t a tus register instruction provides a ccess to the st a tus register. the re a dy/busy a nd write en a ble st a tus of the device c a n be determined by the rd s r instruction. s imil a rly, the block write protection bits indic a te the extent of protection employed. these bits a re set by using the wr s r instruction. table 5. instruction s et for the at2512 8 a/256a instruction name instruction format operation wren 0000 x110 s et write en a ble l a tch wrdi 0000 x100 reset write en a ble l a tch rd s r 0000 x101 re a d s t a tus register wr s r 0000 x001 write s t a tus register read 0000 x011 re a d d a t a from memory arr a y write 0000 x010 write d a t a to memory arr a y table 6. s t a tus register form a t bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wpen x x x bp1 bp0 wen rdy table 7. re a d s t a tus register bit definition bit definition bit 0 (rdy ) bit 0 = ?0? (rdy ) indic a tes the device is re a dy. bit 0 = ?1? indic a tes the write cycle is in progress. bit 1 (wen) bit 1 = 0 indic a tes the device is not write en a bled. bit 1 = ?1? indic a tes the device is write en a bled. bit 2 (bp0) s ee t a ble 8 on p a ge 8 . bit 3 (bp1) s ee t a ble 8 on p a ge 8 . bits 4 ? 6 a re 0s when device is not in a n intern a l write cycle. bit 7 (wpen) s ee t a ble 9 on p a ge 8 . bits 0 ? 7 a re ?1?s during a n intern a l write cycle.
8 at25128a/256a 33 6 8 h? s eepr? 8 /05 write status register (wrsr): the wr s r instruction a llows the user to select one of four levels of protection. the at2512 8 a/256a is divided into four a rr a y segments. top qu a rter (1/4), top h a lf (1/2), or a ll of the memory segments c a n be protected. any of the d a t a within a ny selected segment will therefore be re a d only. the block write protec- tion levels a nd corresponding st a tus register control bits a re shown in t a ble 8 . the three bits, bp0, bp1, a nd wpen a re nonvol a tile cells th a t h a ve the s a me properties a nd functions a s the regul a r memory cells (e.g. wren, t wc , rd s r). the wr s r instruction a lso a llows the user to en a ble or dis a ble the write protect (wp ) pin through the use of the write protect en a ble (wpen) bit. h a rdw a re write protection is en a bled when the wp pin is low a nd the wpen bit is ?1?. h a rdw a re write protection is dis a bled when either the wp pin is high or the wpen bit is ?0?. when the device is h a rd- w a re write protected, writes to the s t a tus register, including the block protect bits a nd the wpen bit, a nd the block-protected sections in the memory a rr a y a re dis a bled. writes a re only a llowed to sections of the memory which a re not block-protected. note: when the wpen bit is h a rdw a re write protected, it c a nnot be ch a nged b a ck to ?0?, a s long a s the wp pin is held low. read sequence (read): re a ding the at2512 8 a/256a vi a the s o pin requires the following sequence. after the c s line is pulled low to select a device, the re a d op-code is tr a nsmitted vi a the s i line followed by the byte a ddress to be re a d (see t a ble 10 on p a ge 9). upon completion, a ny d a t a on the s i line will be ignored. the d a t a (d7 - d0) a t the specified a ddress is then shifted out onto the s o line. if only one byte is to be re a d, the c s line should be driven high a fter the d a t a comes out. the re a d sequence c a n be continued since the byte a ddress is a utom a tic a lly incremented a nd d a t a will continue to be shifted out. when the highest a ddress is re a ched, the a ddress counter will roll over to the lowest a ddress a llowing the entire memory to be re a d in one continuous re a d cycle. table 8. block write protect bits level status register bits array addresses protected bp1 bp0 at25128a at25256a 0 0 0 none none 1(1/4) 0 1 3 000 ? 3 fff 6000 ? 7fff 2(1/2) 1 0 2000 ? 3 fff 4000 ? 7fff 3 (all) 1 1 0000 ? 3 fff 0000 ? 7fff table 9. wpen oper a tion wpen wp wen protected blocks unprotected blocks status register 0 x 0 protected protected protected 0x1protected writ a ble writ a ble 1 low 0 protected protected protected 1low1 protected writ a ble protected x high 0 protected protected protected x high 1 protected writ a ble writ a ble
9 at25128a/256a 33 6 8 h? s eepr? 8 /05 write sequence (write): in order to progr a m the at2512 8 a/256a, two sep a r a te instructions must be exec uted. first, the device must be write enabled vi a the write en a ble (wren) instruction. then a write instruction m a y be executed. also, the a ddress of the memory loc a tion(s) to be progr a mmed must be outside the protected a ddress field loc a tion selected by the block write protection level. during a n intern a l write cycle, a ll comm a nds will be ignored except the rd s r instruction. a write instruction requires the following sequence. after the c s line is pulled low to select the device, the write op-code is tr a nsmitted vi a the s i line followed by the byte a ddress a nd the d a t a (d7 - d0) to be progr a mmed (see t a ble 10). progr a mming will st a rt a fter the c s pin is brought high. (the low-to-high tr a nsition of the c s pin must occur during the s ck low time immedi a tely a fter clocking in the d0 (l s b) d a t a bit. the re a dy/busy st a tus of the device c a n be determined by initi a ting a re a d s t a tus register (rd s r) instruction. if bit 0 = 1, the write cycle is still in progress. if bit 0 = 0, the write cycle h a s ended. only the re a d s t a tus register instruction is en a bled during the write progr a mming cycle. the at2512 8 a/256a is c a p a ble of a 64-byte p a ge write oper a tion. after e a ch byte of d a t a is received, the six low order a ddress bits a re intern a lly incremented by one; the high order bits of the a ddress will rem a in const a nt. if more th a n 64 bytes of d a t a a re tr a nsmitted, the a ddress counter will roll over a nd the previously written d a t a will be overwritten. the at2512 8 a/256a is a utom a tic a lly returned to the write dis a ble st a te a t the completion of a write cycle. note: if the device is not write en a bled (wren), the device will ignore the write instruction a nd will return to the st a ndby st a te, when c s is brought high. a new c s f a ll- ing edge is required to re-initi a te the seri a l communic a tion. table 10. address key address at25128a at25256a a n a 1 3 ? a 0 a 14 ? a 0 don?t c a re bits a 15 ? a 14 a 15
10 at25128a/256a 33 6 8 h? s eepr? 8 /05 timing diagrams (for spi mode 0 (0, 0)) figure 3. s ynchronous d a t a timing figure 4. wren timing figure 5. wrdi timing s o v oh v ol hi-z hi-z t v valid in s i v ih v il t h t s u t di s s ck v ih v il t wh t c s h c s v ih v il t c ss t c s t wl t ho
11 at25128a/256a 33 6 8 h? s eepr? 8 /05 figure 6. rd s r timing figure 7. wr s r timing figure 8. read timing c s s ck 012 3 4567 8 9 1011121 3 14 s i in s truction s o 7654 3 210 data out m s b high impedance 15
12 at25128a/256a 33 6 8 h? s eepr? 8 /05 figure 9. write timing figure 10. hold timing s o s ck hold t cd t hd t hz t lz t cd t hd c s
13 at25128a/256a 33 6 8 h? s eepr? 8 /05 notes: 1. for 2.7v devices used in the 4.5v to 5.5v r a nge, ple a se refer to perform a nce v a lues in the ac a nd dc ch a r a cteristics t a bles. 2. ?u? design a tes green p a ck a ge + roh s compli a nt. 3 .av a il a ble in w a ffle p a ck a nd w a fer form; order a s s l719 for w a fer form. bumped die a v a il a ble upon request. ple a se cont a ct s eri a l eeprom m a rketing. at25128a ordering information (1) ordering code package operation range at2512 8 a-10pi-2.7 at2512 8 an-10 s i-2.7 at2512 8 aw-10 s i-2.7 at2512 8 a-10ti-2.7 8 p 3 8s 1 8s 2 8 a2 industri a l temper a ture ( ? 40 c to 8 5 c) at2512 8 a-10pi-1. 8 at2512 8 an-10 s i-1. 8 at2512 8 aw-10 s i-1. 8 at2512 8 a-10ti-1. 8 8 p 3 8s 1 8s 2 8 a2 industri a l temper a ture ( ? 40 c to 8 5 c) at2512 8 a-10pu-2.7 (2) at2512 8 a-10pu-1. 8 (2) at2512 8 an-10 s u-2.7 (2) at2512 8 an-10 s u-1. 8 (2) at2512 8 aw-10 s u-2.7 (2) at2512 8 aw-10 s u-1. 8 (2) at2512 8 a-10tu-2.7 (2) at2512 8 a-10tu-1. 8 (2) at2512 8 au2-10uu-1. 8 (2) at2512 8 ay4-10yu-1. 8 (2) 8 p 3 8 p 3 8s 1 8s 1 8s 2 8s 2 8 a2 8 a2 8 u2-1 8 y4 le a d-free/h a logen-free/ industri a l temper a ture ( ? 40 c to 8 5 c) at2512 8 a-w2.7-11 ( 3 ) at2512 8 a-w1. 8 -11 ( 3 ) die sa le die sa le industri a l temper a ture ( ? 40 c to 8 5 c) package type 8p3 8 -le a d, 0. 3 00" wide, pl a stic du a l in-line p a ck a ge (pdip) 8s1 8 -le a d, 0.150" wide, pl a stic gull wing s m a ll outline p a ck a ge (jedec s oic) 8s2 8 -le a d, 0.200" wide, pl a stic gull wing s m a ll outline p a ck a ge (eiaj s oic) 8u2-1 8 -b a ll, die b a ll grid arr a y p a ck a ge (dbga2) 8a2 8 -le a d, 4.4 mm body, thin s hrink s m a ll outline p a ck a ge (t ss op) 8y4 8 -le a d, 6.00 mm x 4.90 mm body, du a l footprint, non-le a ded, s m a ll arr a y p a ck a ge ( s ap) options ? 2.7 low-volt a ge (2.7v to 5.5v) ? 1.8 low-volt a ge (1. 8 v to 5.5v)
14 at25128a/256a 33 6 8 h? s eepr? 8 /05 notes: 1. for 2.7v devices used in the 4.5v to 5.5v r a nge, ple a se refer to perform a nce v a lues in the ac a nd dc ch a r a cteristics t a bles. 2. ?u? design a tes green p a ck a ge + roh s compli a nt. 3 .av a il a ble in w a ffle p a ck a nd w a fer form; order a s s l719 for w a fer form. bumped die a v a il a ble upon request. ple a se cont a ct s eri a l eeprom m a rketing. at25256a ordering information (1) ordering code package operation range at25256a-10pi-2.7 at25256an-10 s i-2.7 at25256aw-10 s i-2.7 at25256a-10ti-2.7 8 p 3 8s 1 8s 2 8 a2 industri a l temper a ture ( ? 40 c to 8 5 c) at25256a-10pi-1. 8 at25256an-10 s i-1. 8 at25256aw-10 s i-1. 8 at25256a-10ti-1. 8 8 p 3 8s 1 8s 2 8 a2 industri a l temper a ture ( ? 40 c to 8 5 c) at25256a-10pu-2.7 (2) at25256a-10pu-1. 8 (2) at25256an-10 s u-2.7 (2) at25256an-10 s u-1. 8 (2) at25256aw-10 s u-2.7 (2) at25256aw-10 s u-1. 8 (2) at25256a-10tu-2.7 (2) at25256a-10tu-1. 8 (2) at25256au2-10uu-1. 8 (2) at25256ay4-10yu-1. 8 (2) 8 p 3 8 p 3 8s 1 8s 1 8s 2 8s 2 8 a2 8 a2 8 u2-1 8 y4 le a d-free/h a logen-free/ industri a l temper a ture ( ? 40 c to 8 5 c) at25256a-w2.7-11 ( 3 ) at25256a-w1. 8 -11 ( 3 ) die sa le die sa le industri a l temper a ture ( ? 40 c to 8 5 c) package type 8p3 8 -le a d, 0. 3 00" wide, pl a stic du a l in-line p a ck a ge (pdip) 8s1 8 -le a d, 0.150" wide, pl a stic gull wing s m a ll outline p a ck a ge (jedec s oic) 8s2 8 -le a d, 0.200" wide, pl a stic gull wing s m a ll outline p a ck a ge (eiaj s oic) 8u2-1 8 -b a ll, die b a ll grid arr a y p a ck a ge (dbga2) 8a2 8 -le a d, 4.4 mm body, thin s hrink s m a ll outline p a ck a ge (t ss op) 8y4 8 -le a d, 6.00 mm x 4.90 mm body, du a l footprint, non-le a ded, s m a ll arr a y p a ck a ge ( s ap) options ? 2.7 low-volt a ge (2.7v to 5.5v) ? 1.8 low-volt a ge (1. 8 v to 5.5v)
15 at25128a/256a 33 6 8 h? s eepr? 8 /05 packaging information 8p3 ? pdip 2325 orchard parkway san jo s e, ca 95131 title drawing no. r rev. 8 p 3 , 8-lead, 0.300" wide body, pla s tic d u al in-line package (pdip) 01/09/02 8p3 b note s : 1. thi s drawing i s for general information only; refer to jedec drawing ms-001, variation ba, for additional information. 2. dimen s ion s a and l are mea su red with the package s eated in jedec s eating plane ga u ge gs-3. 3. d, d1 and e1 dimen s ion s do not incl u de mold fla s h or protr us ion s . mold fla s h or protr us ion s s hall not exceed 0.010 inch. 4. e and ea mea su red with the lead s con s trained to b e perpendic u lar to dat u m. 5. pointed or ro u nded lead tip s are preferred to ea s e in s ertion. 6. b 2 and b 3 maxim u m dimen s ion s do not incl u de dam b ar protr us ion s . dam b ar protr us ion s s hall not exceed 0.010 (0.25 mm). common dimen s ion s (unit of mea su re = inche s ) s ymbol min nom max note d d1 e e1 e l b 2 b a2 a 1 n ea c b 3 4 plcs a ? ? 0.210 2 a2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b 2 0.045 0.060 0.070 6 b 3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 ? ? 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc ea 0.300 bsc 4 l 0.115 0.130 0.150 2 top view side view end view
16 at25128a/256a 33 6 8 h? s eepr? 8 /05 8s1 ? jedec soic 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. note: 10/7/03 8s1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 b common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 these drawings are for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.00 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? 0? ? 8? ? top view end view side view e b d a a1 n e 1 c e1 l
17 at25128a/256a 33 6 8 h? s eepr? 8 /05 8s2 ? eiaj soic 2325 orchard parkway san jo s e, ca 95131 title drawing no. r rev. 8s 2 , 8-lead, 0.209" body, pla s tic small o u tline package (eiaj) 10/7/03 8s2 c common dimen s ion s (unit of mea su re = mm) s ymbol min nom max note note s : 1. thi s drawing i s for general information only; refer to eiaj drawing edr-7320 for additional information. 2. mi s match of the u pper and lower die s and re s in bu rr s are not incl u ded. 3. it i s recommended that u pper and lower cavitie s b e e qu al. if they are different, the larger dimen s ion s hall b e regarded. 4. determine s the tr u e geometric po s ition. 5. val u e s b and c apply to p b /sn s older plated terminal. the s tandard thickne ss of the s older layer s hall b e 0.010 +0.010/ ? 0.005 mm. a 1.70 2.16 a1 0.05 0.25 b 0.35 0.48 5 c 0.15 0.35 5 d 5.13 5.35 e1 5.18 5.40 2, 3 e 7.70 8.26 l 0.51 0.85 ? 0 8 e 1.27 bsc 4 end view side view e b a a1 d e n 1 c e1 ? l top view
18 at25128a/256a 33 6 8 h? s eepr? 8 /05 8u2-1 ? dbga2 1150 e. cheyenne mtn. blvd. colorado spring s , co 80906 title drawing no. r rev. po8u2-1 a 6/24/03 common dimen s ion s (unit of mea su re = mm) s ymbol min nom max note 8 u2-1, 8- b all, 2.35 x 3.73 mm body, 0.75 mm pitch, small die ball grid array package (dbga2) a 0.81 0.91 1.00 a1 0.15 0.20 0.25 a2 0.40 0.45 0.50 b 0.25 0.30 0.35 1 d 2.35 bsc e 3.73 bsc e 0.75 bsc e1 0.74 ref d 0.75 bsc d1 0.80 ref 1. dimen s ion ' b ' i s mea su red at the maxim u m s older b all diameter. thi s drawing i s for general information only. d a side view top view bottom view 8 solder ball s 1 a b c d 2 (e1) e a1 ball pad corner (d1) 1. b a1 a2 d a1 ball pad corner e
19 at25128a/256a 33 6 8 h? s eepr? 8 /05 8a2 ? tssop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 5/30/02 common dimensions (unit of measure = mm) symbol min nom max note d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 a ? ? 1.20 a2 0.80 1.00 1.05 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref 8a2 , 8-lead, 4.4 mm body, plastic thin shrink small outline package (tssop) notes: 1. this drawing is for general information only. refer to jedec drawing mo-153, variation aa, for proper dimensions, tolerances, datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07 mm. 5. dimension d and e1 to be determined at datum plane h. 8a2 b side view end view top view a2 a l l1 d 1 2 3 e1 n b pin 1 indicator this corner e e
20 at25128a/256a 33 6 8 h? s eepr? 8 /05 8y4 ? sap 1150 e. cheyenne mtn. blvd. colorado spring s , co 80906 title drawing no. r rev. 8 y4 , 8-lead (6.00 x 4.90 mm body) soic array package (sap) y4 a 8y4 5/24/04 common dimen s ion s (unit of mea su re = mm) s ymbol min nom max note a ? ? 0.90 a1 0.00 ? 0.05 d 5.80 6.00 6.20 e 4.70 4.90 5.10 d1 2.85 3.00 3.15 e1 2.85 3.00 3.15 b 0.35 0.40 0.45 e 1.27 typ e1 3.81 ref l 0.50 0.60 0.70 a e a1 b pin 1 index area d a pin 1 id e1 d1 l e e1
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